The field of invention relates to processor technology generally; and more specifically, to methods and apparatus that may be used for an instruction fetch unit.
Processors are used in computing systems and are implemented within a semiconductor chip. Processors execute instructions in order implement a software program. The instructions used to implement a software program are stored in a memory structure (e.g., an L1 cache, L2 cache and/or system memory) and fetched by the processor prior to their being executed. Each instruction has a corresponding address that is used to obtain the instruction from a particular memory structure location.
FIG. 1 shows a circuit 100 associated with the portion of a processor that fetches instructions. Array 108 has a series of locations 10100 through 101n that each store an instruction address (e.g., instruction addresses ADDRESS1, ADDRESS2 or ADDRESS3). Array 108 serves as a temporary holding place for up to n instruction addresses. The instruction addresses waiting in array 108 have been determined by other logic (not shown in FIG. 1) that determines or otherwise identifies which instructions (from the range of instructions supported by the processor) should be fetched by the processor.
Each instruction address within array 108 has a corresponding RABid value. The RABid value is data structure used to identify which array location 10100 through 101n a particular instruction address is stored in. For example, ADDRESS1 has a corresponding RABid value of xe2x80x9c02xe2x80x9d which reflects the fact that ADDRESS1 is stored in array location 10102. Similarly, ADDRESS2 has a corresponding RABid value of xe2x80x9c04xe2x80x9d which reflects the fact that ADDRESS2 is stored in array location 10104 and ADDRESS3 has a corresponding RABid value of xe2x80x9c00xe2x80x9d which reflects the fact that ADDRESS3 is stored in array location 10100.
For each address offered at input node 102b, the address""s corresponding RABid value is used to control which array location 10100 through 101n will be used to store the address. For example, as seen in FIG. 1, the RABid value is used to select (via the select node 102a) which multiplexor 102 output is enabled for a particular address at input 102b. As another example (not shown in FIG. 1), the multiplexor 102 and its outputs 102c could be respectively replaced with write logic and address/data buses. In this example, the RABid value is used to generate a write address that corresponds to the proper array location. The address is written into the proper array location via the address/data buses.
Eventually an address within array 108 xe2x80x9cissuesxe2x80x9d as an instruction fetch. That is, when the proper moment arrives for an address within array 108 to be used as an instruction fetch from the processor, the proper address is read or otherwise received from its location within array 108 and directed to a memory structure address bus. Array control circuit 107 determines when a particular address is to be issued from the array 108. That is, array control circuit 107 controls: 1) which address is read from array 108; and 2) when the particular address is read from the array 108.
As a basic example, array control circuit 107 stores each xe2x80x9cactivexe2x80x9d RABid (i.e., a RABid currently having an address in its corresponding array 108 location) in a first-in-first-out (FIFO) queue 103. The queue 103 typically has a depth 106 equal to the number xe2x80x9cnxe2x80x9d of array 108 locations. This allows the array control circuit 107 to successfully order the issuing of instruction addresses from array 108 in instances where array 108 is filled.
The RABids are stored in the queue 103 in the order in which they are used to store addresses in array 108. For example, if ADDRESS1 was first to arrive at input 102b followed by ADDRESS2 and then ADDRESS3, the queue 103 stores the RABids in the following order: RABid:02, RABid:04, RABid:00. Thus RABid:02 is serviced before RABid:04 and RABid:04 is serviced before RABid:00.
When a RABid is serviced from queue 103, its value is used to issue the RABid""s corresponding instruction address. That is, RABid:02 will be used to issue ADDRESS1 from array location 10102, RABid:04 will be used to issue ADDRESS2 from array location 10104 and RABid:00 will be used to issue ADDRESS3 from array location 10100. This is accomplished by directing each RABid value from queue 103 to a unit that controls the issuing of address from array 108. For example, as seen in FIG. 1, the RABid is coupled to the selection control 104a of a multiplexor 104. Alternatively (not shown in FIG. 1), the multiplexor 104 and its inputs 104a could be respectively replaced with read logic and address/data buses. In this example, the RABid value from queue 103 is used to generate a read address that corresponds to the proper array location. The address is read from the proper array location via the address/data buses. The number of outstanding issues are controlled by queue control circuit 105. When an instruction is successfully fetched, the RABid value used for its address is returned to array control circuit 107. Thus, if the current number of outstanding issues is at its maximum allowable value, the queue control circuit 105 can trigger the servicing of the next RABid in queue 103 upon the return of a previously serviced RABid value.
An apparatus is described comprising a signal indicative of which of a plurality of data structures stored in a queue desire to issue from the queue. The apparatus also has a content addressable memory having a plurality of cells, where each of the cells is configured to store one of the data structures. The apparatus also has an output from at least one of the cells that is indicative of whether the data structure within the at least one of the cells has issued from the queue. The apparatus also has an input to the at least one of the cells coupled to the signal.